With advancement in technologies, people's lives are getting increasingly convenient. In work or in entertainment, people cannot do without electronic products. In view of the trend, many products are developed to make people enjoy the convenience brought by the electronic products.
In addition, because the functions of modern electronic products, for example, the third-generation (3G) mobile phones, are more and more powerful, manufacturers spend all their strength on integrating new functions, such as MP3 players, digital cameras, GPS, TV systems, broadcasting systems, image short messages, video phones, and credit card functions, to cellular phones. When more functions are integrated, the quality and quantity requirements on power supplies are raised accordingly. On the other hand, cellular phones are becoming gradually into consumables in the market, easy to be replaced with a short life cycle. If the product is not developed in the shortest time to meet the demands of consumers, then the profit margin will definitely shrink. Thereby, engineers must be acquainted with the advantages and disadvantages of various power management ICs as well as with the usage methods thereof, so that maximum profit margins can be created in the shortest time.
Charge pumps based on switched capacitors are utilized in the power management of current general portable devices. Because of their relatively low EMI/EMC, they are widely applied to various electronic products particularly handheld electronic products such as PDAs and cellular phones. With the development of handheld electronic products, different functions are gradually integrated into a single chip (SOC). The voltage levels of the power supplies in the chips are diverse. In general, the battery of a handheld electronic product can only supply a single voltage Vsup of around 2.7V. Due to functional requirements of the products, it is necessary to convert the around-2.7V voltage to various voltages by means of a charge pump. Voltage doublers and voltage inverters are utilized most frequently. FIGS. 1A and 1B show a circuit diagram and timing diagrams of a doubler charge pump according to the prior art, respectively. As shown in the figure, the circuit comprises a first switch 10′, a pump capacitor 11′, a second switch 12′, a third switch 13′, a fourth switch 14′, an output capacitor 15′, a first buffer 20′, a second buffer 21′, a third buffer 22′, and a fourth buffer 23′. The first switch 10′ is coupled to a supply voltage VDD and a first terminal of the pump capacitor 11′. A second terminal of the pump capacitor 11′ is coupled to the second and third switches 12′, 13′. The second switch 12′ is coupled between the supply voltage VDD and the second terminal of the pump capacitor 11′. The third switch 13′ is coupled between the second terminal of the pump capacitor 11′ and the ground. The fourth switch 14′ is coupled between the first terminal of the pump capacitor 11′ and a terminal of the output capacitor 15′. The output capacitor 15′ is coupled between the fourth switch 14′ and the ground. The buffers 20′, 21′, 22′, 23′ are coupled to the first, the second, the third, and the fourth switches 11′, 12′, 13′, 14′, respectively, for controlling the switches. The output of the doubler charge pump is approximately twice the supply voltage VDD, which is around 2.7V.
If the reliability of fabrication is allowed, generally, 5V-MOS devices are used to implement the switched-capacitor charge pumps. The gate-to-source voltage (VGS) of the MOS device used as capacitor switch is only Vsup. When the drain-to-source voltage (VDS) is known small, that is, VDS<<2(VGS−Vth), the relation between the on-resistance (RMOS) of a MOS switch and VGS is:RMOS ∝ [(W/L)*(VGS−Vth)]−1, when VDS<<2(VGS−Vth)where W is the channel width of the MOS switch, L is the channel length of the MOS switch, and Vth is the threshold voltage of the MOS switch. In FIG. 1B, the input and output waveforms of the inverting buffers are shown. Assuming the threshold voltage of the 5V PMOS is −Vthp and the threshold voltage of the 5V NMOS is Vthn, according to the equation described above, the on-resistances of the first, the second, the third, and the fourth switches 11′, 12′, 13′, 14′ are
                                          R                          MOS              ,                              10                ′                                              ∝                    ⁢                                    [                                                (                                                            W                                                                        10                          ′                                                ⁢                        1                                                              /                                          L                                              10                        ′                                                                              )                                *                                  (                                                                                                          V                                                  GS                          ,                                                      10                            ′                                                                                                                                      -                    Vthp                                    )                                            ]                                      -              1                                                                    =                    ⁢                                    [                                                (                                                            W                                              10                        ′                                                              /                                          L                                              10                        ′                                                                              )                                *                                  (                                      VDD                    -                    Vthp                                    )                                            ]                                      -              1                                                                                    R                          MOS              ,                              12                ′                                              ∝                    ⁢                                    [                                                (                                                            W                                              12                        ′                                                              /                                          L                                              12                        ′                                                                              )                                *                                  (                                                                                                          V                                                  GS                          ,                                                      12                            ′                                                                                                                                      -                    Vthp                                    )                                            ]                                      -              1                                                                    =                    ⁢                                    [                                                (                                                            W                                              12                        ′                                                              /                                          L                                              12                        ′                                                                              )                                *                                  (                                      VDD                    -                    Vthp                                    )                                            ]                                      -              1                                                                                    R                          MOS              ,                              13                ′                                              ∝                    ⁢                                    [                                                (                                                            W                                              13                        ′                                                              /                                          L                                              13                        ′                                                                              )                                *                                  (                                                            V                                              GS                        ,                                                  13                          ′                                                                                      -                    Vthn                                    )                                            ]                                      -              1                                                                    =                    ⁢                                    [                                                (                                                            W                                              13                        ′                                                              /                                          L                                              13                        ′                                                                              )                                *                                  (                                      VDD                    -                    Vthn                                    )                                            ]                                      -              1                                                                                    R                          MOS              ,                              14                ′                                              ∝                    ⁢                                    [                                                (                                                            W                                              14                        ′                                                              /                                          L                                              14                        ′                                                                              )                                *                                  (                                                                                                          V                                                  GS                          ,                                                      14                            ′                                                                                                                                      -                    Vthp                                    )                                            ]                                      -              1                                                                    =                    ⁢                                    [                                                (                                                            W                                              14                        ′                                                              /                                          L                                              14                        ′                                                                              )                                *                                  (                                                            Output                      ⁢                                                                                          ⁢                      1                                        -                    Vthp                                    )                                            ]                                      -              1                                                                    =                    ⁢                                    [                                                (                                                            W                                              14                        ′                                                              /                                          L                                              14                        ′                                                                              )                                *                                  (                                      AVDD                    -                    Vthp                                    )                                            ]                                      -              1                                                                    =                    ⁢                                    [                                                (                                                            W                                              14                        ′                                                              /                                          L                                              14                        ′                                                                              )                                *                                  (                                                            2                      *                      VDD                                        -                    Vthp                                    )                                            ]                                      -              1                                          According to the equations above, it is known that the on-resistances of the first, the second, and the third switches 11′, 12′, 13′ are inversely proportional to (VDD−Vth), and thereby are greater than that of the fourth switch. Hence, greater power will be consumed, and worse output voltage level is given. Besides, greater circuit areas will be needed during IC fabrication.
Likewise, FIG. 2A shows a circuit diagram and timing diagrams of an inverting charge pump according to the prior art. As shown in the figure, the difference between FIG. 2A and FIG. 1A is that in the present figure, a fifth switch 30′ is coupled to the ground, a fifth buffer 32′ is coupled to the fifth switch 30′ and receives input signals ranging from the supply voltage VDD to a negative supply voltage VCL, and a sixth buffer 34′ is coupled to the sixth switch 36′ and receives input signals ranging from the supply voltage VDD to a negative supply voltage VCL. The fifth switch 30′, a seventh switch 38′, and an eighth switch 39′ have the same problems of the circuit in FIG. 1A.
Accordingly, the present invention provides a novel charge pump capable of enhancing power efficiency and output voltage, which utilizes 2*Vsup as VGS of the MOS device used for switching the capacitor. Thereby, the on-resistance of the MOS device is reduced effectively while improving the power efficiency of the charge pump, the output voltage level, and the area efficiency of integrated circuits.